Static Random Access Memory (SRAM) cells comprise an increasing portion of modern very large scale integrated (VLSI) circuits. A conventional SRAM cell 10 is illustrated in FIG. 1. As illustrated, the SRAM cell 10 includes pull-down transistors M1 and M3, pull-up transistors M2 and M4, and access transistors M5 and M6 connected as shown. The SRAM cell 10 is written differentially, with one bit line (e.g., BL) at a high potential and the other bit line (e.g., BLN) at a low potential. A write operation is performed by driving a voltage level corresponding to a desired logic value onto the bit line (BL) and/or its converse onto the bit line not (BLN) while asserting a word line (WL) to turn-on the access transistors M5 and M6. As a result, the desired logic value is stored at output node C, and a complementary logic value is stored at output node CN. During a write operation, the access transistor M5 must overpower the pull-up transistor M2 (i.e., the SRAM cell 10 is a ratioed circuit during writes). Adequate write margin is ensured by sizing the access transistor M5 to be stronger than the pull-up transistor M2. The write margin is typically defined in one of two ways. The direct current (DC) approach is to measure the bit line (BL) voltage required to flip the state of the SRAM cell 10 (i.e., flip the output node C from storing a logic “1” to a logic “0” or vice versa) by keeping one of the bit lines (e.g., BL) high and lowering the other bit line (e.g., BLN) from VDD towards VSS until the state of the SRAM cell 10 is flipped. Alternatively, a delay to write the SRAM cell 10 when the bit line (BL) is driven to VSS may be measured.
A read operation is performed by pre-charging the bit line (BL) and the bit line not (BLN) to a high voltage level and asserting the word line (WL) to a high voltage level in order to turn on the access transistors M5 and M6. If a logic “0” is stored at the output node C, the pull-up transistor M2 is off and the pull-down transistor M1 is on. Due to the voltage division across the transistors M1 and M5, the voltage at the output node C rises above VSS. This rise in voltage at the output node C decreases a Static Noise Margin (SNM) of the SRAM cell 10 during the read operation. The rise in voltage at the output node C when reading a logic “0” is determined by the cell ratio of the gate size of the pull-down transistor M1 to that of the access transistor M5. The higher the cell ratio, the smaller the voltage drop across the pull-down transistor M1 and the greater the SNM of the SRAM cell 10. Thus, the pull-down transistor M1 must be stronger than the access transistor M5 so that a logic “0” stored at the output node C is not pulled high enough to flip the cell during a read operation. Similarly, the pull-down transistor M3 must be stronger than the access transistor M6 so that a logic “0” stored at the output node CN is not pulled high during a read operation. However, there is a conflicting restraint that the pull-up transistors M2 and M4 be weaker than the access transistors M5 and M6 in order to ensure write-ability, thereby constraining the design space for the conventional (six transistor) SRAM cell 10.
One issue with the SRAM cell 10 is that the SRAM cell 10 must typically be tested to determine whether the SRAM cell 10 meets desired read and/or write margins. For a single SRAM cell 10, such testing is fairly simple. However, an issue arises in conventional SRAM circuits, which include thousands to millions of SRAM cells 10. A conventional SRAM circuit includes multiple banks of SRAM cells 10. Each bank of SRAM cells 10 includes numerous columns of SRAM cells 10 that are typically arranged into column groups. The number of SRAM cells 10 in each bank may be on the order of hundreds, thousands, or more. In each bank, only one SRAM cell 10 per column group can be accessed (read or written) at a time. Thus, testing of the write margin and/or read SNM of the SRAM cells 10 in each of the banks requires a significant amount of time.
Therefore, there is a need for systems and methods that enable fast testing of SRAM circuitry.